Field of the Invention
This invention relates to a character and graphic signal generating apparatus, and more particularly to such an apparatus of the type suitable for use with a personal computer for displaying characters and graphic patterns in a superposed relation according to a raster scan method.
Personal computers which are quickly spreading now in the field of office automation are generally connected to a CRT display unit of the raster scan type. In most of such personal computers, both character and graphic patterns are displayed on the display screen of the CRT display unit so as to deal with multipurpose uses. Among them, the type which displays characters and graphic patterns in a superposed relation is highly appreciated from the aspects of display effect and utility.
A system having a construction as, for example, shown in FIG. 1 has been proposed as a practical means for realizing the desired function described above. Referring to FIG. 1, the system includes a clock signal generating unit 1, a display address generating unit 3, a central microprocessor unit 40 (abbreviated hereinafter as an MPU), an MPU data bus 7, a graphic page register 8, a high-order address switching unit 10, an MPU display address switching unit 14, a readable and writable memory for display 16 (abbreviated hereinafter as a display RAM), a graphic data latch 17, a character data latch 18, a character pattern generating unit 19, a composite video signal generating unit 20 and a CRT display unit 21. In FIG. 1, reference numerals 2, 4, 5, 6, 9, 11, 12, 13 and 15 designate a display clock signal, a display low-order address signal, a raster number signal, a character high-order address signal, a graphic page selection signal, a high-order address switching signal, a display high-order address signal, an MPU address signal flowing through an address bus, and an MPU display switching signal, respectively.
The signal flow in FIG. 1 will now be described. On the basis of the display clock signal 2 generated from the clock signal generating unit 1, the display address generating unit 3 generates the display low-order address signal 4, raster number signal 5 and character high-order address signal 6 all of which are updated in each character display period. In response to the application of the high-order address switching signal 11 switching over between the former half and the latter half of one character display period, the high-order address switching unit 10 generates the display high-order address signal 12. In the former half of the character display period, this output signal 12 is the character high-order address signal 6 applied from the display address generating unit 3, and, in the latter half of the character display period, this output signal 12 is the graphic high-order address signal which is the combination of the raster number signal 5 applied from the display address generating unit 3 and the graphic page selection signal 9 applied from the graphic page register 8. On the basis of the MPU display switching signal 15, the MPU display address switching unit 14 applies the MPU address signal 13 to the display RAM in the MPU cycle and applies the display low-order address signal 4 and the display high-order address signal 12 to the display RAM 16 in the display cycle. Among the data read out from the display RAM 16 in the display cycle, that data read out in the former half of one character display period is latched in the character data latch 18, and that data read out in the latter half of one character display period is latched in the graphic data latch 17. The output signal from the character data latch 18 is converted into a character pattern signal by the character pattern generating unit 19 to which the raster number signal 5 is applied, and the character pattern signal is then applied to the composite video signal generating unit 20. On the other hand, the graphic pattern signal which is the output signal from the graphic data latch 17 is also applied to the composite video signal generating unit 20, and, after processing including parallel-serial conversion and superposition, the output signal from the composite video signal generating unit 20 is applied to the CRT display unit 21 to provide a visual display on the display screen.
FIG. 2 shows the memory map of the display RAM 16. This display RAM is composed of a parallel array of eight 64-kilobit dynamic RAMs such as, for example, those of model HM4864 made by the Hitachi, Ltd. to provide a memory having a capacity of 64 kilobytes. The former half having the capacity of 32 kilobytes is allotted to the graphic memory region, and the latter half having the capacity of 32 kilobytes is allotted to the character memory region. In FIG. 2, one page means one frame displayed on the CRT display unit 21. In the illustrated memory map, one page of character display corresponds to the capacity of 2 kilobytes capable of displaying 80 characters.times.25 lines, and there are 16 pages ranging from the page No. 0 to the page No. 15 for character display. One page of graphic display includes 16 kilobytes which is 8 times as large as that for character display, and this corresponds to the capacity capable of displaying 640.times.200 dots in one frame.
Table 1 shows the manner of allocation of 16 address bits A15 to A0 to the display RAM 16 in the display cycle. The most significant bit A15 is the bit which assigns whether the region is the former-half graphic memory region of 32 kilobytes or the latter-half character memory region of 32 kilobytes. Therefore, this bit A15 is always in the level "L" in the graphic display cycle, that is, in the latter half of one character display period and is always in the level "H" in the character display cycle, that is, in the former half of one character display period. In the graphic display cycle, the address bit A14 assigns the graphic page selection signal 9 applied from the graphic page register 8 to the high-order address switching unit 10, and the address bits A13 to All assign the raster number signal 5 applied to the high-order address switching unit 10. On the other hand, in the character display cycle, the address bits A14 to All assign the character high-order address signal 6 applied to the high-order address switching unit 10. The address bits A10 to A0 are common to both of the graphic display cycle and the character display cycle, and the display low-order address signal 4 is applied to the MPU display address switching unit 14.
TABLE 1 ______________________________________ Memory address Graphic Character bit display cycle display cycle ______________________________________ A15 Always "L" Always "H" A14 Graphic page selec- Character tion signal 9 high-order address signal 6 A13-A11 Raster number signal 5 A10-A0 Display low-order address signal 4 ______________________________________
According to the above method, the display address generating unit 3 and the display RAM 16 are provided in common to both of the character display and the graphic display, so that the overall cost and the number of parts can be reduced. However, in view of the fact that the character high-order address and the graphic high-order address are inevitably different from each other, the method is defective in that these address signals must be applied to the common display RAM 16 in a time division mode. In the case of the large-capacity, low-cost 64-kilobit dynamic RAM described above, its shortest cycle time is 270 ns. Therefore, the minimum access time required for reading in one character display period is 540 ns representing the sum of those for character data and graphic data. Even when the common low-order address bits are allotted to columns and the technique of access-time shortening called the page mode peculiar to the dynamic RAM is employed, 500 ns is considered to be the practical limit of one character display period when various margins are taken into account. In this case, the function of graphic display resolution that can be realized with one frame scanning frequency of 60 Hz which is sufficiently high compared with the afterglow time of a conventional CRT display unit is about 640 dots in the horizontal direction and 280 dots in the vertical direction.
On the other hand, in order to meet the recent requirement for display of kanji (Chinese characters), a higher resolution of about 640 dots.times.400 dots is required for practical use. The prior art method described above is defective in that it can not meet such a requirement.